This invention relates to methods for processing semiconductor materials, and in particular to methods for measuring the amount of alignment offset problems in the fabrication of a semiconductor which exist between an interconnect layer and a layer having openings therein such as vias or the like, and provides for effective and efficient electrical and visual alignment confirmation of the location of the openings.
Semiconductor integrated circuits undergo a variety of processing steps during manufacture, such as masking, resist coat, etching, and deposition. In many of these steps, material is overlaid or removed from the existing layer at specific locations in order to form the desired elements of the integrated circuit. Proper alignment of the various process layers is therefore critical. The shrinking dimensions of modem integrated circuits require increasingly stringent overlay alignment accuracy. If the proper alignment tolerance is not achieved, a device can result which is defective or has reliability problems.
More specifically, semiconductor processes such as described above employ fabrication steps in which aligned openings are formed in contact layers to complete an electrical connection. The interconnect layer is typically a metal layer and the contact layer or via layer is typically an insulating/dielectric layer.
There is thus a need that exists for reducing alignment offset problems between an interconnect layer and the layer containing the openings.